1. Field of the Invention
The present invention relates to semiconductor devices and methods for producing the devices, and particularly to a semiconductor device including a transistor having a damascene gate and a resistor and a method for producing the device.
2. Description of the Related Art
A damascene process is used to form a wiring line in a method for producing a semiconductor device.
In the damascene process, for example, a wiring line is formed by forming a wiring-line groove in an insulating film on a substrate, depositing a conductive material in the wiring-line groove, and removing the conductive material deposited outside the groove by a method such as chemical mechanical polishing (CMP) without removing the conductive material deposited inside the groove.
Metal-oxide-semiconductor field-effect transistors (MOSFETs or MOS transistors), a basic element of a semiconductor device, have increasingly been miniaturized to produce semiconductor devices with smaller sizes and higher packing densities. To keep up with such scaling, a reduction in gate length and the thickness of a gate insulating film has been demanded.
SiON-based insulating films, which have been used as gate insulating films, may no longer be suitable for use as gate insulating films because they cause increased leakage in generations of 32-nm design rules or later.
Accordingly, the use of high-k films as gate insulating films has been studied for their potential to have increased physical thickness.
A typical high-k film has low heat resistance and should therefore be formed after a high-temperature diffusion heat treatment for source and drain regions.
One method enabling this process is a damascene-gate process in which the above damascene process is used to form a gate electrode of a MOS transistor, as disclosed in, for example, Japanese Unexamined Patent Application Publication No. 8-335701 and Yamaguchi et al., “High Performance Duel Metal Gate CMOS with Mobility and Low Threshold Voltage Application to Bulk CMOS Technology”, 2006 Symposium on VSLI Technology Digest of Technical Papers, IEEE, 2006, Vol. 6, pp. 192-193. According to another method, a gate electrode and a resistor are formed using the same material.
Referring to FIG. 6A, according to an example of a damascene-gate process in which a gate electrode and a resistor are formed using the same material, a dummy gate insulating film 112a and a dummy gate electrode 113a are formed in an active region defined in a semiconductor substrate 110 by an isolation insulating film 111, that is, by shallow trench isolation (STI). The dummy gate insulating film 112a and the dummy gate electrode 113a are used as a mask to form source/drain regions 114 by ion implantation.
At the same time as the formation of the dummy gate insulating film 112a and the dummy gate electrode 113a, a silicon oxide film 112b and a polysilicon layer 113b are formed on the isolation insulating film 111 using the same materials.
Next, an interlayer insulating film 115 is formed by depositing silicon oxide over the entire surface of the semiconductor substrate 110, including those of the dummy gate electrode 113a and the polysilicon layer 113b, by a method such as chemical vapor deposition (CVD). The top of the interlayer insulating film 115 is then polished by CMP until the surfaces of the dummy gate electrode 113a and the polysilicon layer 113b are exposed.
Referring to FIG. 6B, the dummy gate electrode 113a and the polysilicon layer 113b are removed by etching, and the dummy gate insulating film 112a and the silicon oxide film 112b are removed.
Thus, a gate-electrode groove 115a and a resistor groove 115b are formed in the interlayer insulating film 115.
Referring to FIG. 6C, a silicon oxide film is deposited over the surface of the semiconductor substrate 110, including the inner surfaces of the gate-electrode groove 115a and the resistor groove 115b, by a method such as CVD. A conductive layer is then deposited over the silicon oxide film so as to fill the gate-electrode groove 115a and the resistor groove 115b by a method such as CVD. The silicon oxide film and the conductive layer deposited outside the gate-electrode groove 115a and the resistor groove 115b are removed by a treatment such as CMP.
Thus, a gate insulating film 116a formed of the silicon oxide film and a gate electrode 117a formed of the conductive layer can be embedded in the gate-electrode groove 115a while a resistor 117b can be embedded in the resistor groove 115b with a silicon oxide film 116b disposed therebetween.
The damascene-gate process thus allows formation of a gate insulating film with low heat resistance after a high-temperature process. This provides the advantage of extending the range of options of conductive materials for gate electrodes because they are formed after the high-temperature process.
For the damascene-gate process, resistors such as those used for analog circuits are often formed at a large line width, for example, about 1 to 10 μm, so that variations in resistance can be suppressed. Such a large line width, however, results in formation of a dishing D, as shown in FIG. 6C, on the surface of the conductive layer constituting the resistor 117b after the CMP.
A dishing is a phenomenon by which a material embedded in a wide or large groove by a method such as CVD or sputtering is thinned toward the center of the groove after CMP planarization due to the characteristics of CMP.
In a damascene-gate process, a larger dishing occurs in a larger groove, due to the characteristics of CMP, because the CMP is performed on the final stage of the step of forming a gate electrode and a resistor.
In addition, variations due to the CMP itself contribute to variations in the size of the dishing.
Thus, a dishing occurs on a conductive layer when a resistor is formed by a damascene-gate process, and variations in the size of the dishing result in variations in the resistance of the resistor. This makes it difficult to form a resistor with high accuracy which is suitable for an analog circuit.